Job Details:
Key Responsibilities
Architectural Leadership: Evaluate trade-offs across features, performance targets, power constraints, and system limitations.
Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/System Verilog, integrate at top level, and deliver synthesis- and timing-clean designs.
Verification Collaboration: Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
Timing & Physical Design Support: Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.
Silicon Bring-Up: Drive post-silicon validation, debug, and performance analysis.
Mentorship & Methodology: Mentor junior engineers and contribute to best practices for design methodology and quality.
Additional Responsibilities
Perform quality checks across RTL, timing, and power convergence.
Apply secure development practices to address security threat models and objectives.
Collaborate with IP providers for integration and validation at the SoC level.
Drive compliance for smooth IP-to-SoC handoff.
Additional Skills:
Ability to lead projects, work cross-functionally, and deliver under tight schedules
Strong communication skills and a collaborative mindset
Qualifications:
Minimum Qualifications
Bachelor's or master's degree in electrical engineering, Computer Engineering, or Computer Science or related field with 10+ years of experience.
7+ years of experience in RTL design and implementation for ASIC/SoC development.
Preferred Qualifications
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
Hands-on experience with SoC system integration and multicore CPU subsystem design.
Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
Expertise in high-speed and low-power design techniques.
Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
Familiarity with industry-standard EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, Folsom
Additional Locations:
US, California, Santa Clara, US, Texas, Austin
Business group:
Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
