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选择求职条件负责量子比特控制的物理设计工作，涵盖RTL到GDS全流程，推动综合、布局布线与时序收敛。深耕低温控制设计的后端方法学，与CAD及定制IP团队协同优化PPA指标。
Job Description:
As a Qubit Control Physical Design Engineer, you will drive or participate in the following:
• Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals.
• Will be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield.
• Will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in cryogenic control design.
• Will drive physical implementation through synthesis, formal verification, floor planning, bus / pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO and sign-off.
• Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA.
• Contribute to developing physical design methodologies.
Minimum Qualifications
• Bachelor’s, Master’s, or Ph.D. degree, with 8+ years of relevant experience. • Qualified experience may have been gained through professional employment, academic institutions, research activities, university projects, coursework, or other comparable educational and professional endeavors.
• Experience with logic design and digital circuits.
• Experience in Python, PERL/TCL, Linux/Unix shell and C.
Preferred Qualifications
• Experience in low power, high frequency physical design techniques leveraging advanced syn/PnR tool features, and best in class physical design methodology.
• Experience using industry standard logic Synthesis, PnR, STA and Power analysis tools, along with timing budgeting, floor-planning, physical integration, and verification to converge complex designs.
• Knowledge in deep sub-micron technology, along with its implications to timing, power, and area.
• Excellent communication and interpersonal skills.
• Ability to work independently and/or lead a physical design partition in collaboration with cross functional teams.
• Experience with DFT and DFM flows.
• Ability to provide mentorship, guidance to junior engineers and be a very effective team player.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.负责领导尖端SoC设计的验证工作，制定仿真、仿真加速及形式化验证策略，确保流片一次成功。指导验证团队，定义可扩展方法论，影响Intel技术方向，弥合微架构规范与硅片实现之间的差距。
