R&D Engineering, Engineer

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&
D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are
You are a passionate software engineer with a strong background in algorithms and system-level thinking. You enjoy solving complex problems and are driven to build scalable and efficient backend solutions for large-scale hardware systems.

What You'll Be Doing
- Develop and optimize multi-FPGA partitioning algorithms for the ZeBu emulation compile flow, going beyond pure cut-size minimization
- Build timing-aware partitioning solutions that incorporate critical path timing criticality into partition cost models and optimization objectives
- Account for ZeBu clocking constraints —such as driver-clock-driven user clocks via multi-cycle paths—when evaluating partition quality and feasibility
- Design and enhance a more robust partitioning engine that reduces sensitivity to random initial solutions in traditional hMetis-based flows
- Apply analytical partitioning approaches to improve initial solution quality, stability, and reproducibility
- Work on constraint-aware partitioning for logic/memory resources, inter-FPGA connectivity, and timing-related partition constraints
- Collaborate closely with the FPGA P&
R and runtime teams to validate partitioning decisions and support ZeBu platform sign-off
- Analyze partitioning bottlenecks and implement scalable, maintainable C/C++ backend components on Linux

The Impact You Will Have
- Improve emulation performance by making partitioning timing-aware, not just cut-size driven
- Increase partitioning robustness and reproducibility by reducing dependence on random initial solutions
- Improve partition quality and compile outcomes for large SoC designs through a more stable partitioning engine
- Enable successful ZeBu platform sign-off by delivering partitioning solutions validated with FPGA P&
R and runtime teams
- Advance state-of-the-art emulation partitioning by combining classical graph partitioning with analytical optimization techniques

What You'll Need
- Bachelor's or master's degree in computer science, Electrical Engineering, or a related field
- Strong foundation in algorithms, data structures, and graph/hypergraph partitioning
- Experience with C/C++ and performance-oriented software development on Linux/Unix. Script languages like python, tcl are plus.
- Knowledge of optimization techniques and partitioning algorithms (e.g., hMetis, multi-way partitioning, heuristic and analytical methods)
- Understanding of timing-aware optimization or willingness to develop expertise in timing-critical partitioning
- Preferred: Basic exposure to clock synthesis or multi-cycle path concepts, to better reason about timing-related partition constraints
- Preferred: Background in analytical approaches to partitioning or large-scale optimization (e.g., spectral, eigenvector-based, or other mathematically grounded methods)
- Strong problem-solving, debugging, and experimental evaluation skills

Who You Are
- Analytical and detail-oriented
- Passionate about algorithm design and performance optimization
- Self-motivated and able to work independently
- A strong team player with good communication skills
- Eager to learn and adapt to new technologies

The Team You'll Be Part Of
You will be part of a highly skilled R&
D team working on backend software for emulation systems. The team collaborates closely with global hardware verification engineering teams to deliver high-performance solutions and continuously push the boundaries of verification technology.

Rewards and Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits
- Health &
Wellness: Comprehensive medical and healthcare plans that work for you and your family.
- Time Away: In addition to company holidays, we have ETO and FTO Programs.
- Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement Plans: Save for your future with our retirement plans that vary by region and country.
- Compensation: Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm