以上为北京时间。链接检查不代表仍在招聘，申请前请以招聘官网为准。
按这个岗位的城市和方向提醒，确认后才开启，可选择每日或每周。
负责存储控制器及DRAM测试引擎等创新项目的设计与开发，理解系统需求并制定规格说明。使用Verilog/SystemVerilog实现高性能、低面积、低功耗RTL设计，完成IP级仿真、回归测试、综合及时序收敛。支持验证团队进行测试设计及调试，并负责LINT、CDC、综合等集成活动。
Responsible for designing and developing various innovative projects, including the Memory Controller and DRAM Test Engine projects etc.
Understand the system requirements of the digital functions and develop specifications.
Microarchitecture of RTL code aimed for high performance, low area and low power design. Implement the function in Verilog or System Verilog according to specification. Perform IP level simulation and regression test with the design modules.
Perform IP level synthesis and timing closure. Optimize the design for high performance, low area and low power.
Support the DV team by providing design insights for test plan design and test design, debugging and fixing failing test cases and writing self-checking tests as required.
Support all design integration activities like LINT, CDC, synthesis and logical equivalence etc.
MS in Electrical Engineering, Computer Engineering or related field and one (1) year experience
Research and development of digital IPs
RTL coding in Verilog
Digital IP microarchitecture design
Simulation tools and methodology such as UVM
Code management tools such as SVN
软件和信息技术服务业
