以上为北京时间。链接检查不代表仍在招聘，申请前请以招聘官网为准。
按这个岗位的城市和方向提醒，确认后才开启，可选择每日或每周。
负责逻辑设计、合成、时序分析或验证测试覆盖工作，需具备计算机体系结构专业知识。设计岗需Verilog RTL实现经验，验证岗需掌握UVM等先进方法。
Logic Design and Verification Engineer
DG001
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Logic design/synthesis/timing analysis or Logic Verification/Test Coverage
Responsible for design or verification, and presentation documents
Requirements:
MS EE/CS or BS EE/CS+2 years of experience
Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools
Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog
Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM
Team player and an optimist: able to work with teams in multiple office sites Plus Skills:
Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI.
Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller
Fluent in System Verilog, SVA, C++ or assembly language
Experience with FPGA/emulator (Palladium/Veloce)
To apply, please send resume with Job ID
included in the subject to: jobs@flctechgroup.com
MS EE/CS or BS EE/CS+2 years of experience
Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools
Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog
Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM
Team player and an optimist: able to work with teams in multiple office sites Plus Skills:
Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI.
Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller
Fluent in System Verilog, SVA, C++ or assembly language
Experience with FPGA/emulator (Palladium/Veloce)
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