以上为北京时间。链接检查不代表仍在招聘，申请前请以招聘官网为准。
按这个岗位的城市和方向提醒，确认后才开启，可选择每日或每周。
负责SoC设计及芯片调试全流程，与各团队协作交付PCIe硬件解决方案，完成微架构设计、复杂逻辑实现及仿真平台上的软硬件协同验证。
Responsible for all aspects of SoC design and chip bring up. Work with members of the SoC Design and Verification, System Verification, Firmware, Emulation, and Physical Design teams. Deliver working PCIe hardware solutions within the SoC Develop micro-architecture and design specifications. Implement and verify complex logic designs. Hands-on verification and validation on emulation platforms running with the SW drivers.
MS EE/CS+5 year of experience or PhD EE/CS. Experience of PCIe root complex and end points. Verilog RTL logic design experience of multi-million gate ASICs. Experience writing specifications and converting them to design. Experience with bring up and lab debug of FPGAs prototyping and silicon. Experience with commercial PCIe/CXL IPs such as Synopsys. Good communication with IP vendors. Plus Skills: Experience in NVMe. Knowledge of various DMA architectures. Knowledge of next-gen interconnect fabric protocol (OpenCAPI, CXL, CCIX, GenZ).
软件和信息技术服务业
