以上为北京时间。链接检查不代表仍在招聘,申请前请以招聘官网为准。
按这个岗位的城市和方向提醒,确认后才开启,可选择每日或每周。
岗位城市暂未明确,请先到找职位页面选择城市和方向。
选择求职条件负责下一代高性能低功耗CPU微架构设计与RTL实现,重点关注功耗管理与能效优化。主导CPU IP模块的SystemVerilog/Verilog开发,推动PPA优化、多时钟域及CDC方案设计,并参与DVFS、电源/热管理及复位流程等特性开发。
About the Role
Join Intel’s CPU Design Team within the Silicon & Platform Engineering (SPE) Group, where you will help architect and deliver next-generation, power-efficient, high-performance processors.
As a Senior CPU RTL Design Engineer – Power Management, you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient design. This role is ideal for engineers who can contribute with minimal ramp-up and bring deep expertise in low-power CPU/SoC design.
You will partner closely with architecture, verification, and physical design teams to deliver industry-leading silicon.
What You’ll Do
Behavioral Traits that we are looking for:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Note:
For information on Intel’s immigration sponsorship guidelines, please see
Intel U.S. Immigration Sponsorship Information
Minimum Qualifications and Experience:
Bachelor's degree in Electrical/Computer Engineering, Computer Science or related filed with 9+ years of relevant experience. Or a Master's degree in the same field with 7+ years of experience.
You experience mentioned above must be in the following:
Preferred Qualifications and Experience:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.负责领导尖端SoC设计的验证工作,制定仿真、仿真加速及形式化验证策略,确保流片一次成功。指导验证团队,定义可扩展方法论,影响Intel技术方向,弥合微架构规范与硅片实现之间的差距。