DDR Design Verification Engineer, Staff

We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are
You have spent years in verification and you know that catching a bug before tape-out is the difference between a product launch and a very expensive respin. DDR is your domain. You have read JEDEC specs not because you had to, but because you wanted to understand why the protocol works the way it does. You think in timing diagrams and corner cases, and you have built enough testbenches to know when a verification plan is missing something critical.
You do not just run regressions, you understand what broke, why it broke, and whether it matters. When a design team tells you something should work, you ask the right questions and find the edge case they did not consider. You have worked in UVM long enough to know its strengths and where it gets in the way, and you adapt your strategy accordingly.
Mentorship matters to you. You have guided junior engineers through their first testbench or helped them debug a failure that looked impossible, and you find satisfaction in watching them grow. At Synopsys, you will work on DDR5 and LPDDR6 IP that powers the next generation of memory subsystems, and the verification strategies you build will directly determine whether those products ship on time.

What You'll Be Doing
Lead verification efforts for DDR5 and LPDDR6 IP, owning the verification plan from microarchitecture study through regression closure
Study and interpret JEDEC specifications to build comprehensive test scenarios that cover protocol compliance, performance, and corner cases
Develop and maintain UVM-based verification environments, including testbenches, scoreboards, checkers, and coverage models
Debug complex RTL and testbench issues, trace failures across design and verification code, and work with design teams to resolve root causes
Analyze regression results, triage failures, identify patterns, and drive coverage closure across functional and code metrics
Collaborate with VIP teams to integrate and configure verification IP for DDR protocols, AXI, CHI, and related interfaces
Mentor junior verification engineers, review their code and test plans, and help them build skills in UVM methodology and debugging techniques

The Impact You Will Have
Your verification strategies will directly determine whether DDR5 and LPDDR6 IP products meet quality and schedule commitments for tape-out
The bugs you catch before silicon will save millions in respin costs and protect customer schedules across multiple product lines
Your test plans and coverage models will become the foundation for future DDR IP verification efforts across the team
The UVM infrastructure you build will enable faster verification cycles and higher quality for the next generation of memory IP
Your mentorship will accelerate the growth of junior engineers and raise the overall verification capability of the team
Your collaboration with design and VIP teams will surface microarchitecture issues early, reducing costly late-stage design changes
The regression analysis and triage processes you establish will improve debug efficiency and reduce time to root cause across the project

What You'll Need
Master's degree in Electrical Engineering, Computer Engineering, or a related technical field
5+ years of hands-on experience with UVM-based verification on complex digital IP or SoC projects
Deep understanding of DDR protocols, specifically DDR5 or LPDDR6, including JEDEC specification details and compliance requirements
Strong RTL debugging skills using simulation tools and waveform analysis to trace complex functional failures
Proven ability to develop verification plans, build UVM testbenches, and drive coverage closure on production IP
Experience with AXI, CHI, CRYPTO, or RAS protocols is a strong plus
Scripting experience in Shell, Perl, Python, or TCL for automation and regression analysis is a plus

Who You Are
You can read a JEDEC spec, spot the ambiguity or edge case that is not explicitly covered, and build a test that targets it
When a regression fails at 3am before a milestone, you do not panic, you methodically narrow the scope, reproduce the issue, and find the root cause
You review a junior engineer's testbench and can explain not just what is wrong, but why it matters and how to think about verification architecture differently
You push back when a verification plan is incomplete or a design assumption has not been validated, and you do it in a way that moves the conversation forward
You are comfortable working across time zones with design teams in different locations, adapting your communication style to get alignment without endless meetings
You treat verification like a product, you think about maintainability, reusability, and whether the next person who touches your code will understand what you built

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.