以上为北京时间。链接检查不代表仍在招聘,申请前请以招聘官网为准。
按这个岗位的城市和方向提醒,确认后才开启,可选择每日或每周。
负责模拟/定制版图设计,包括布局规划、匹配优化、敏感信号布线等,涉及SerDes、USB、DDR等高速PHY版图。要求本科及以上,熟练使用Virtuoso XL等工具。
Custom Layout Design Engineer
Position Description:
Responsible for custom layout floorplan, matching guides, resistor/capacitor placement, reduce coupling & noise, sensitive signals routing, mix-signals routing, etc.
Responsible for custom layout top level hierarchy floorplan for blocks/powers
Responsible for high-speed mixed-signal PHY such as SerDes, USB, DDR, etc
Responsible for cooperation with analog circuit design team to ensure high efficiency and quality for analog layout design.
Position Requirements:
BSEE degree with 2+ years of applicable experience in analog/custom layout of advanced technology nodes
Proficient with Layout edit/verify tools, like Virtuoso XL, Pegasus/Calibre DRC/LVS, etc.
Proficient with EMIR tools, like Voltus-FI
Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
Fundamental understanding of IC design technology and process/methodology
Essential that the individual demonstrates good teamwork and self-motivation
Good communication skills in English
Work experience in PERC run is a plus
Work experience in FinFET layout is a plus
Work experience in ESD/Latch-up is a plus
Work experience in cooperation with digital P&R team is a plus
软件和信息技术服务业