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负责SoC/ASIC芯片全流程数字物理实现，包括综合、布局布线、CTS、静态时序分析、物理验证及电源IREM分析。需与前端、IP和封装团队协作。要求微电子或EE专业硕士毕业生，熟悉VLSI基础和TCL脚本。
【Job Description】
We are recruiting outstanding fresh graduates majoring in Microelectronics or EE , to join Digital physical design team. Candidate will participate in full digital physical implementation flow, including synthesis/floorplan/placement/cts/routing/STA/PhyV/Power IREM for advanced SOC and ASIC projects. Trainings and project experiences are provided for candidates as well.
【Responsibilities】
1. Full-flow digital physical design , including Synthesis, Floorplan, CTS, Routing and PostRoute optimization.
2. Static Timing Analysis, timing closure, including setup/hold/and other miscellaneous check fixing.
3. Physical verification including DRC/LVS/Antenna/ERC/Perc/DFM.
4. Power IREM analysis and fixing for chip robustness and yield improvement.
5. Work closely with Front-End team,IP team and Package Team to solve cross function issues.
6. Scripting productively for flow maintenance and efficiency improvement.
【Requirement】
1. MS in Microelectronics/EE or related majors , 2026 fresh graduates.
2. Logical thinking, patient and rigorous work attitude, strong problem-solving ability ,good team work and communication skills.
3. Solid understanding of VLSI, Timing Constraints, Solid Circuit, semiconductor physical design basics.
4. Familiar with full backend implementation flow.
5. TCL Scripting; basic Python is preferred.
6. Good English skills is preferred.
软件和信息技术服务业
