以上为北京时间。链接检查不代表仍在招聘，申请前请以招聘官网为准。
按这个岗位的城市和方向提醒，确认后才开启，可选择每日或每周。
Cadence招聘Virtuoso工程师，为foundry团队提供模拟后端流程技术支持，涵盖原理图、布局及PDK开发与验证。要求电子工程或计算机本科及以上学历，3年以上IC设计或晶圆厂工作经验。
Provide technical support for Virtuoso‑based analog backend flows, including schematic, layout, and design environment usage.
Assist in PDK usage and enablement from a foundry perspective, ensuring correct adoption of process rules and recommended flows in Virtuoso.
Assist foundry teams in the development and maintenance of Virtuoso technology files (techfiles), PCells, and related QA flow.
Work with product engineers and R&D teams to communicate customer issues and feedback, and help track resolution under guidance from senior engineers.
Participate in foundry‑related customer engagements as needed, focusing on tool usage, flow clarification, and issue reproduction.
Bachelor’s degree(EE/CS) with 3+ years of work experience in IC design house or foundry. MS degree is desired
软件和信息技术服务业
