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选择求职条件负责定义下一代CPU端到端电源管理架构,制定主动和空闲电源管理方案,与操作系统、驱动及平台组件交互。加入英特尔顶级芯片能效技术团队,主导创新技术方案从设计到硅后实现。
Power management architect for Intel Architecture group, take part in the definition of the state-of-the-art CPU end to end power handling. Defines active and idle power management solutions, interaction with OS, driver and platform components. You will acquire understanding in CPU architecture and micro architecture, deep understanding in power scenarios, power delivery and power efficiency schemes. The primary focus of this position is to define next generation CPU power management architecture, deliver architectural specifications. You will initiate, guide and coordinate overall design of new ideas and products, drive for implementation and activation in post Si.
Intel is in the world's top leaders of chip power and energy management. You will join part of experienced technical architecture leading team, inventing and driving innovative technologies solutions at Intel and Industry
Bachelor's degree in Electrical Engineering, Computer Engineering or related field 6+ years of related work experience
Experience in SW writing and definition (C/C++,python, C#) OR experience in aspects of Chip design and a development (electrical components, logical flows, CPU architecture).
Deep understanding in system architecture and state of the art CPU design for PC or mobile devices
Ability to deal with ambiguity, strong analytics and problem solving skills to achieve high quality results; Strong interpersonal skills (with proven track record of cross group collaboration)
Self-motivated, customer oriented, resourceful and enthusiastic, showing an intense customer mind-set.
Strong debugging experience and excellent problem solving skills.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
负责领导尖端SoC设计的验证工作,制定仿真、仿真加速及形式化验证策略,确保流片一次成功。指导验证团队,定义可扩展方法论,影响Intel技术方向,弥合微架构规范与硅片实现之间的差距。