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选择求职条件负责模拟与混合信号IC设计,包括线缆IO AFE、时钟和稳压器电路,集成到Intel先进工艺测试芯片中。与工艺和IP团队紧密合作,推动下一代工艺技术和产品开发。
The Group: Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) focuses on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits to enable best-in-class Foundational IP collateral and product design across all generations of Intel process technology. Critical technologies AD-FIP delivers to Intel are Digital and Analog Standard Cell Libraries, Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High-speed I/O Reference Designs (DDR, UCIe, PCIe, SerDes, GPIO), RF and Wireless Circuits (Wave Guide TX, Power Amplifier).
As an analog and mixed-signal IC designer your day-to-day responsibilities will include, but not always be limited to:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
The qualifications listed below must meet the required years of experience associated with the candidate’s degree level:
Preferred Qualifications:
Experience in one or more of the following areas is preferred:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.负责领导尖端SoC设计的验证工作,制定仿真、仿真加速及形式化验证策略,确保流片一次成功。指导验证团队,定义可扩展方法论,影响Intel技术方向,弥合微架构规范与硅片实现之间的差距。